TSMC Weighs 20% CoWoS Price Hike Amid AI Chip Demand
Taiwan Semiconductor Manufacturing Company is reportedly evaluating a significant price increase for its advanced packaging technology as surging demand for artificial intelligence processors strains global manufacturing capacity.
Radwan AbdulhadiEditor and technology writer
Advanced Packaging Capacity Under Severe Pressure
Taiwan Semiconductor Manufacturing Company (TSMC) is reportedly weighing a price increase of up to 20% for its Chip on Wafer on Substrate (CoWoS) advanced packaging technology. According to details highlighted by Tom's Hardware through reports from Trendforce, the potential price hike reflects heavily strained capacity driven by relentless artificial intelligence demand and longer delivery times for crucial chipmaking tools.
CoWoS technology combines logic dies and high-bandwidth memory (HBM) stacks into a single package, providing the critical data bandwidth required by demanding AI workloads. Building these sophisticated packages continues to grow more complex as hardware designers integrate larger amounts of compute power and memory into their products.
The Impact of Nvidia Blackwell and Rubin Accelerators
The demand surge is heavily propelled by cutting-edge hardware architectures. Nvidia’s Blackwell already pairs two massive graphics processing units with eight HBM3E memory stacks, while the upcoming Rubin and Rubin Ultra chips are anticipated to push integration levels even further, multiplying the operational strain on the advanced packaging supply chain.
Furthermore, testing procedures have emerged as another major operational bottleneck. Reports indicate that Blackwell chips require three to four times longer to test than the previous-generation Hopper architecture, and upcoming Rubin chips could demand as much as seven times longer. Extended test cycles mean production equipment remains occupied for longer periods, complicating efforts to scale output alongside climbing market demand.
Longer Equipment Lead Times and Supply Chain Strains
The operational squeeze extends directly to manufacturing machinery. Equipment lead times have reportedly stretched from an earlier window of three to six months out to as long as eight months. Ensuring timely access to essential fab tools has become a paramount priority for the manufacturer.
As a result of these elongated timelines, TSMC reportedly placed its current equipment orders at existing market prices rather than negotiating typical volume discounts or extra concessions. This strategy marks a clear shift from its customary approach of leveraging strong purchasing power, demonstrating that securing timely tool deliveries now outweighs cost-reduction efforts.
Broader Wafer Price Adjustments Expected for 2027
Cost increases will likely not remain restricted to advanced packaging services alone. TSMC is reportedly considering broader pricing adjustments for 2027, with wafer prices across advanced process technologies expected to rise by 5% to 10%. Customers utilizing 2nm and 3nm-class nodes could encounter the most substantial baseline hikes.
Additionally, buyers seeking manufacturing capacity that exceeds their original allocations may face additional financial premiums, potentially driving total cost increases up to as much as 25% for certain clients. Industry estimates indicate that monthly wafer capacity targets are scaling significantly to handle the broader AI chip surge, though hardware costs across the supply chain are widely expected to climb as a result.
Sources
- Tom's HardwareTSMC reportedly weighs 20% CoWoS price increase as Nvidia Blackwell and Rubin chips put pressure on packaging capacity — equipment lead times stretch to eight months
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