OpenAI Deploys Jalapeño ASICs with AMD EPYC Turin Hosts
OpenAI has selected AMD EPYC Turin processors to act as hosts for its rack-scale Jalapeño ASICs, bypassing Nvidia's standalone Vera due to platform maturity considerations.
Radwan AbdulhadiEditor and technology writer
Pragmatic Architecture Choices for Jalapeño
OpenAI has chosen to pair its new Jalapeño ASIC internally with AMD EPYC Turin hosts, each equipped with 1.5TB of memory. Following public descriptions of the rack-scale deployment, Tom's Hardware conducted an interview with Richard Ho, VP and Head of Hardware at OpenAI, to discuss the hardware architecture choices behind the program. As detailed in the interview regarding the we asked Richard Ho, VP and Head of Hardware at OpenAI, about in an interview., the decision to leverage Turin was described as a pragmatic move aimed at ensuring performance and cost goals without taking unnecessary risks.
According to Ho, the primary goal of the Jalapeño program design phase was de-risking and moving swiftly. While the market features various high-performance agentic chips and Arm-based architectures, OpenAI opted for a solution built on a mature foundation. The x86_64 ecosystem benefits from decades of deep operational roots, providing a reliable choice for enterprise and data center workloads.
Evaluating Platform Maturity and Nvidia's Vera
When questioned about the choice of Turin given OpenAI's close working relationship with Nvidia, Ho explained that Nvidia's custom data center CPU offering was not yet the ideal fit for this particular deployment. He noted that Vera, as a standalone option, is currently a little bit behind on that maturity level compared to established x86 alternatives. Furthermore, OpenAI's partners possessed prior operational experience with the Turin device, helping streamline the development cycle.
The semiconductor industry has seen intense messaging surrounding server CPUs and evolving agentic workloads, with companies like Nvidia positioning their Arm-based Vera against x86 competitors. Early benchmarks for Vera have appeared impressive, but the hardware represents Nvidia's first foray into a custom CPU core for the data center, making it a riskier choice for OpenAI's immediate rack-scale Jalapeño goals.
Socketed Flexibility Versus Board-Mounted Hardware
Another practical element influencing OpenAI's hardware strategy involves the physical maintenance and servicing of the host systems. Practical differences exist between Turin and Vera, notably that Vera chips are board-mounted whereas Turin processors are socketed. Although swapping server processors in the field is uncommon, socketed designs like Turin offer added flexibility for engineering teams during testing and deployment phases.
The maturity of x86_64 relative to newer 64-bit Arm implementations also played a role. Although Arm architectures have expanded significantly within hyperscaler data centers over the past two decades through custom chips like AWS Graviton and Google Cloud's Axiom, the decades-long foundation of x86 provided a predictable ecosystem for OpenAI's timeline.
Future Deployment Potential
Although Turin serves as the current host system for Jalapeño, OpenAI maintains a diverse fleet of computing hardware. Industry observers note that the inference ASIC could potentially be paired with alternative host systems in future iterations, such as Arm's AGI or Nvidia's Vera, as those architectures mature and gain broader enterprise validation.
For the initial rollouts of the Jalapeño architecture, however, the combination of performance, cost parameters, and ecosystem familiarity made AMD's EPYC Turin the most reliable selection for OpenAI's hardware engineering division.
Sources
- Tom's HardwareOpenAI’s Jalapeño ASICs are deployed alongside AMD EPYC ‘Turin’ CPUs as hosts, not Nvidia's Vera
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