China's DUV Chipmaking Stretched Without EUV
China's chipmaking industry has stretched older DUV lithography to approach 5nm-class nodes without EUV, though experts highlight mounting trade-offs in manufacturing costs, yields, and die sizes.
Radwan AbdulhadiEditor and technology writer
The Challenge of EUV Export Restrictions
Export controls have kept ASML's most advanced EUV lithography machines out of China, creating a technological gap that analysts estimate is at least half a decade wide. The advanced machines, produced exclusively by the Dutch manufacturer, utilize 13.5nm-wavelength light to print intricate features required for modern processors. Because the sale of these systems is subject to strict export restrictions, Chinese semiconductor firms have had to find alternative paths.
Instead of utilizing extreme ultraviolet equipment, the country's domestic chipmaking industry has relied heavily on older deep ultraviolet (DUV) lithography machines. By applying multiple exposures across critical layers, these older systems are still capable of producing functional silicon. However, applying multiple patterns significantly raises the chances of defects, lengthens manufacturing schedules, and increases overall production bills.
Pushing DUV to 5nm-Class Densities
Despite lacking access to EUV tools, domestic advancements have surprised observers. Teardowns of Huawei’s Mate 60 Pro revealed a Kirin 9000S processor manufactured by SMIC utilizing a second-generation 7nm-class process without EUV equipment. More recent analysis of Huawei’s Kirin 9030 indicates that SMIC has driven its DUV-based manufacturing even closer to the density levels typical of 5nm production, though it still falls short of industry leaders like TSMC and Samsung.
The core technique behind this progress is multiple patterning. Rather than attempting to print complex chip layouts in a single pass, manufacturers divide intricate designs into simpler patterns. Repeating this process iteratively etches layers that approximate the intended structures. Industry experts, including Chris Mack, co-founder and CTO of the semiconductor firm Fractilia, point out that evaluating these achievements requires looking past simple milestone claims.
Economic and Yield Trade-Offs
While multiple patterning works, it introduces substantial economic and operational penalties. Conventional industry wisdom long held that three exposures on a 193 immersion tool cost roughly the same as a single EUV exposure. According to Mack, once production shifts to four masks to replace a single EUV mask, EUV becomes significantly more cost-effective.
Furthermore, each additional exposure increases the risk of misalignment. Every time a wafer receives a new pattern, it must align precisely with everything etched beneath it. Accumulating process variations across multiple masks leave more opportunities for errors. To mitigate these risks, designers often leave wider margins around circuit features, resulting in larger die sizes that rapidly escalate production costs per wafer.
Memory Versus Logic Manufacturing Realities
Evidence of this efficiency gap is visible in memory production. Morgan Stanley estimated in a June report that Chinese DRAM manufacturer CXMT produced roughly one-third as many bits per wafer as Western competitors. Researchers like Douglas Fuller from the Copenhagen Business School note that while engineering workarounds exist for advanced logic chips, they remain inefficient and costly.
In contrast, memory manufacturing presents a different set of opportunities. Micron successfully developed its 1-alpha DRAM generation using DUV and multiple patterning without EUV, proving that highly repetitive memory structures make close coordination between design and manufacturing easier. Nevertheless, even Micron eventually adopted EUV for its newer 1-gamma process to secure higher bit density, highlighting the eventual limits of stretching DUV for complex logic processors.
Sources
- Tom's HardwareChina can make advanced chips without EUV, but the bill keeps growing
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